manuais National CP3BT26

National CP3BT26 Manual do Utilizador (278 páginas)

Marca: National | Categoria: Hardware | Tamanho: 4.11 MB |

Inglês

Índice

Bluetooth

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, USB, and CAN Interfaces

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Table of Contents

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2.0 Features

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3.0 Device Overview

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3.21 POWER MANAGEMENT

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3.22 DMA CONTROLLER

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3.23 SERIAL DEBUG INTERFACE

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3.24 DEVELOPMENT SUPPORT

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4.0 Signal Descriptions

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5.0 CPU Architecture

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5.5 ADDRESSING MODES

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5.6 STACKS

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5.7 INSTRUCTION SET

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6.0 Memory

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8.0 Flash Memory

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8.3 FLASH MEMORY OPERATIONS

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8.4 INFORMATION BLOCK WORDS

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8.5 FLASH MEMORY INTERFACE

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REGISTERS

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9.0 DMA Controller

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9.3 OPERATION MODES

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9.4 SOFTWARE DMA REQUEST

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9.5 DEBUG MODE

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The upper 8 bits of the AD

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– Channel inactive

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10.0 Interrupts

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10.5 NESTED INTERRUPTS

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11.0 Triple Clock and Reset

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11.1 EXTERNAL CRYSTAL NETWORK

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11.2 MAIN CLOCK

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11.3 SLOW CLOCK

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11.4 PLL CLOCK

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12.0 Power Management

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13.0 Multi-Input Wake-Up

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13.2 PROGRAMMING PROCEDURES

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14.0 Input/Output Ports

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– Slow slew rate

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– Fast slew rate

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14.2 OPEN-DRAIN OPERATION

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15.0 Bluetooth Controller

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15.2 SERIAL INTERFACE

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D0D14A0A1A2A3A4WH0H1H2 D15

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D0D1A0A1A2A3A4RH0H1H2 D15

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Description

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16.1 FUNCTIONAL DESCRIPTION

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16.2 TOUCHSCREEN INTERFACE

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16.4 FREEZE

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16.5 ADC REGISTER SET

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17.1 FREEZE

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17.2 RANDOM NUMBER GENERATOR

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REGISTER SET

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18.0 USB Controller

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18.2 ENDPOINT OPERATION

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18.3 USB CONTROLLER REGISTERS

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—This mode is

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—Setting this bit al

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—The TOGGLE

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—The TOGGLE bit

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—This bit indi

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—This bit is set if a

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—A value of 0 in

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—This bit reflects

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18.4 TRANSCEIVER INTERFACE

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19.0 CAN Module

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19.2 BASIC CAN CONCEPTS

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19.3 MESSAGE TRANSFER

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19.4 ACCEPTANCE FILTERING

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19.5 RECEIVE STRUCTURE

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+ CONTROL

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19.7 INTERRUPTS

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19.8 TIME STAMP COUNTER

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19.9 MEMORY ORGANIZATION

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→ RX_BUSY0.)

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→ RX_BUSY1.)

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→ RX_BUSY2.)

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19.12 USAGE HINT

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20.0 Advanced Audio Interface

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TXDSA = 1

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TXDSA = 0

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RXDSA = 1

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RXDSA = 0

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20.3 BIT CLOCK GENERATION

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20.4 FRAME CLOCK GENERATION

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20.6 COMMUNICATION OPTIONS

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21.1 OPERATION

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21.2 PCM CONVERSIONS

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21.8 FREEZE

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. If set, this bit en

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22.0 UART Modules

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22.3 UART REGISTERS

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22.4 BAUD RATE CALCULATIONS

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23.0 Microwire/SPI Interface

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23.2 MASTER MODE

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23.3 SLAVE MODE

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23.4 INTERRUPT GENERATION

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24.0 ACCESS.bus Interface

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24.4 USAGE HINTS

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25.1 TWM STRUCTURE

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25.2 TIMER T0 OPERATION

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25.3 WATCHDOG OPERATION

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25.4 TWM REGISTERS

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25.5 WATCHDOG PROGRAMMING

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PROCEDURE

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26.0 Multi-Function Timer

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26.2 TIMER OPERATING MODES

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26.3 TIMER INTERRUPTS

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26.4 TIMER I/O FUNCTIONS

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26.5 TIMER REGISTERS

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27.2 VTU REGISTERS

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28.0 Register Map

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29.0 Register Bit Fields

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30.1 ABSOLUTE MAXIMUM RATINGS

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30.6 OUTPUT SIGNAL LEVELS

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30.7 CLOCK AND RESET TIMING

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Figure 110. Clock Timing

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Figure 111. NMI Signal Timing

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Figure 113. Power-On Reset

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30.8 UART TIMING

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30.9 I/O PORT TIMING

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30.11 MICROWIRE/SPI TIMING

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30.12 ACCESS.BUS TIMING

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Figure 128. ACB Data Timing

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30.16 EXTERNAL BUS TIMING

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31.0 Pin Assignments

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(LQFP-144)

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32.0 Revision History

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